The present invention generally relates to integrated circuit chip (IC) carrier connector assemblies, and more particularly to those assemblies requiring high chip density (i.e., a high number of chips per unit area) and ease of chip removability.
Most types of chip carriers used for mounting integrated circuits ("ICs") to other assemblies require a substrate area larger than the IC itself in order to accommodate input and output ("IO") connection mechanisms to the IC. In part, this has been the case because of the low pin densities achievable using current technologies. In the past, standard mounting assemblies have included dual and single in-line packaging types (commonly referred to as "DIPs" and "SIPs", respectively) and more recently pin grid array packages and leadless chip carriers having interconnection pads that are reflow soldered or are socketed around their perimeter.
In IC mounting assemblies, it is often desirable to reduce the size of the chip carrier and interconnection mechanism such that the ratio of chip carrier substrate to IC area is as small as possible. This is particularly important in electro-optical devices, where chips bearing optically sensitive ICs must be closely spaced over an area, as well as other devices where high chip density is required for low total volume and weight, such as space borne applications. The packing efficiency of such chip carrier assemblies is often measured in terms of I/O channels (e.g., pins or pads) per chip carrier area. Current DIP or pin grid array chip carriers maximally hold about 30 to 70 IOs per square inch, while the area of the substrate supporting the IC and interconnect assembly range from approximately 12 to 16 times larger than that of the IC itself.
Such IC chip carrier devices generally use either solder or some mechanical closing device to affix the chip carrier to the mother board or other assembly. These connecting schemes have the disadvantage that they are either bulky, requiring an increase in the area of the chip carrier required to support the IC, or that they are difficult to remove and reconnect.
It is, accordingly, a primary object of the present invention to provide an improved integrated circuit chip carrier apparatus where the area taken by the chip carrier may be as small as that of the chip itself, and where the chip carrier may be easily detached and reconnected to a higher level assembly.